1. Field of the Invention
This invention relates to a method for the production of a semiconductor device and more particularly to a method for the production of a semiconductor device which is possessed of a ferroelectric capacitor.
2. Description of the Prior Art
FRAM (ferroelectric random access memory) is known as an non-volatile semiconductor memory device and it comprises a plurality of memory cells each composed of a capacitor provided with a ferroelectric layer and a n type MOS transistor. A lead titanate zirconate [Pb(Zr.sub.x Ti.sub.1-x)O.sub.3 ] film is one example of the ferroelectric layer.
Now a standard process for the formation of one of the memory cells of the FRAM will be described below. The lead titanate zirconate will be hereinafter referred to as PZT.
First, an isolated n type MOS transistor 2 is formed on a silicon substrate 1 as illustrated in FIG. 1A.
This n type MOS transistor 2 is formed in a region enclosed with a field oxide 6 on the surface of the silicon substrate 1 and is composed of a gate electrode 4 formed on the silicon substrate 1 through the medium of a gate insulating layer 3 and a source region 5s and a drain region 5d formed in the silicon substrate 1 beside the gate electrode 4. The source region 5s and the drain region 5d are formed by ion implantation such an n type impurity as phosphorus or arsenic into the silicon substrate with the gate electrode 4 as a mask and then annealing the silicon substrate 1 for activation.
This gate electrode 4 constitutes itself part of a word line WL. This part of the word line WL is so formed as to pass on the field oxide 6.
After the n type MOS transistor 2 and the word line WL have been formed as described above, an interlayer insulating layer 7 for covering the n type MOS transistor 2 and the word line WL is formed as illustrated in FIG. 1B. BPSG (boro-phospho siilicate glass) grown by the CVD is used, for example, for the interlayer insulating layer 7.
Next, the process needed to produce the state illustrated in FIG. 1C will be described.
When a first platinum (Pt) layer 8 and a PZT layer 9 are sequentially grown in the order mentioned on the interlayer insulating layer 7 which overlies the field oxide 6 adjoining the n type MOS transistor 2, the resultant superposed layers are annealed in an atmosphere of oxygen to crystallize the PZT layer 9. A second Pt layer 10 is subsequently formed on the PZT layer 9.
Thereafter, the second Pt layer 10 is patterned by the dry etching method using an etching gas and a resist mask. The patterned second Pt layer 10 is used as the upper electrode of a capacitor. Since this etching deteriorates the quality of the PZT layer 9, the superposed layers existent at this point is annealed in an atmosphere of oxygen to supply oxygen through the second Pt layer 10 to the PZT layer 9.
The PZT layer 9 is further patterned in the shape of a dielectric layer of the capacitor by the dry etching method using a resist mask. The first Pt layer 8 is subsequently patterned in the shape of a lower electrode of the capacitor by the dry etching method using a resist mask. In each of these etching operations, the superposed layers are annealed in an atmosphere of oxygen to supply oxygen through the second Pt layer 10 to the PZT layer 9.
The patterning of the capacitor is thus completed.
Then, a protective insulating layer 11 of SiO.sub.2 is wholly grown by the method of vapor-phase growth using tetra ethoxy silane (TEOS). Subsequently, the protective insulating layer 11 is patterned to form a first and a second opening 11a, 11b as illustrated in FIG. 1D so as to expose the second Pt layer 10 (upper electrode) through the first opening 11a and, at the same time, expose the lower electrode through the second opening 11b.
Thereafter, for the recovery of PZT layer quality, the resultant superposed layers are annealed in an atmosphere of oxygen to supply oxygen through the second Pt layer 10 to the PZT layer 9.
Further, the protective insulating layer 11 and the interlayer insulating layer 7 are patterned to form a third opening 11g for exposing the gate electrode 4 (word line WL), a fourth opening lid for exposing the drain region 5d, and a fifth opening 11s for exposing the source region 5s as illustrated in FIG. 1E.
Subsequently, an aluminum layer is formed throughout the entire surface and this aluminum layer is patterned by the method of photolithography to form wirings 12a, 12b, 12s, 12d, and 12g as illustrated in FIG. 1F.
The steps described above result in forming the memory cell of the FRAM.
In these steps, after the PZT layer 9 is annealed for the sake of crystallization, the component layers are annealed four times in the atmosphere of oxygen for the purpose of supplying oxygen to the PZT layer 9. The reason for the necessity of the repeated annealing is that the PZT layer will suffer the ferroelectricity thereof to be impaired when it is degraded by the hydrogen in the etching gas and consequently depleted of oxygen. Incidentally, the Pt layer permits relatively easy passage of hydrogen and oxygen when it has a thickness of the order of several hundreds of nm.
In the process described above, the formation of the first and second openings 11a and 11b and the formation of the third through fifth openings 11g, 11s, and 11d, both intended for preventing the source region 5s and the drain region 5d of the n type MOS transistor from being oxidized during the annealing operation in the atmosphere of oxygen, are carried out at separate steps.
When the openings to be formed in the same insulating layer are produced at two steps, since the positions for the formation of the first and second openings and those for the formation of the third through fifth openings are liable to deviate relative to one another, the alignment of wirings in these openings will become difficult and the yield will be possibly degraded.